Please use this identifier to cite or link to this item: http://hdl.handle.net/1880/45694
Title: THE VLSI IMPLEMENTATION OF A FINE-GRAINED PARALLEL ARCHITECTURE
Authors: Williams, Simon Richard
Keywords: Computer Science
Issue Date: 1-Jun-1990
Abstract: This thesis evolved out of a fine-grained parallel processor designed by John Cleary. The design was improved to increase the speed and provide testability. The resultant design was then implemented as a VLSI layout. Estimates of power consumption and clocking speeds were then derived from the layout using SPICE simulations. Evaluation shows that the power estimate is within practical limits of chip operation when packaged. Issues of fanout, metal migration, and supply line noise are also addressed.
URI: http://hdl.handle.net/1880/45694
Appears in Collections:Williams, Mike

Files in This Item:
File Description SizeFormat 
1990-391-15.pdf13.55 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.