THE DESIGN OF AN INSTRUCTION STREAM MEMORY SUBSYSTEM
Abstract
Artificial Intelligence (AI) is emerging as the dominant application area
to be supported by next-generation computers. The dramatic performance
improvements necessary to enable this support can only come about through
a complete reorganization of conventional architectures and problem
solving techniques. Most present-day systems are organized around a
complex processing element coupled to a simple, unstructured memory. The
purpose of this thesis is to investigate an alternative memory organization
termed the Instruction Stream Memory of ISM. This memory is designed
as a system part for a highly replicated, ultra-concurrent next
generation AI machine architecture. The intent is to improve performance
by distributing into the memory itself many of the functions associated with
the accessing and processing of an instruction stream, such as next
address calculation, instruction pre-fetch, and branch processing. This
frees the processor from these tasks and reduces the severity of the
processor-memory bottleneck. A possible design for the ISM, targeted for
implementation as a custom CMOS chip, is presented.
Description
Keywords
Computer Science