CONNECTIONIST ARCHITECTURES

dc.contributor.authorCleary, John G.eng
dc.date.accessioned2008-02-27T16:56:15Z
dc.date.available2008-02-27T16:56:15Z
dc.date.computerscience1999-05-27eng
dc.date.issued1986-03-01eng
dc.description.abstractMany schemes for computing have been proposed and variously described as distributed, connectionist, neuron-like and massively parallel. These are difficult to implement in current technology because at the circuit level they imply very complex wiring or switching and at the system level they cannot be efficiently simulated on a traditional von Neumann computer. A VLSI based architecture which avoids some of these problems is proposed. The basic operation implemented is the weighted summing of signals from a large number (~1000) inputs using the $sum$-chip. Signals are heavily multiplexed, and the weighting coefficients are stored in shift registers on the same chip that does the summing. The result is a VLSI chip which has two ingoing signal pins and one outgoing. As an example a system using the $sum$-chip is described which solves the n-Queens logical puzzle. Its application in chess playing is also considered briefly.eng
dc.description.notesWe are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at digitize@ucalgary.caeng
dc.identifier.department1986-234-8eng
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/30536
dc.identifier.urihttp://hdl.handle.net/1880/45817
dc.language.isoEngeng
dc.publisher.corporateUniversity of Calgaryeng
dc.publisher.facultyScienceeng
dc.subjectComputer Scienceeng
dc.titleCONNECTIONIST ARCHITECTURESeng
dc.typeunknown
thesis.degree.disciplineComputer Scienceeng
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