THE ARCHITECTURE OF HENDERSON'S SECD MACHINE

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dc.contributor.authorSimpson, T.eng
dc.contributor.authorBirtwistle, G.eng
dc.contributor.authorHermann, M.eng
dc.contributor.authorGraham, B.eng
dc.date.accessioned2008-05-26T20:33:01Z
dc.date.available2008-05-26T20:33:01Z
dc.date.computerscience1999-05-27eng
dc.date.issued1989-01-01eng
dc.description.abstractWe explain and document the architecture of an eager SECD machine devised by Henderson. A software interpreter for this architecture has been in use for two years and has been well tested. Expansion of the interpreter leads to the detailed specifications of an architecture in VLSI. Such an SECD chip has been layed out and fabricated.eng
dc.description.notesWe are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at digitize@ucalgary.caeng
dc.identifier.department1989-340-02eng
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/30393
dc.identifier.urihttp://hdl.handle.net/1880/46593
dc.language.isoEngeng
dc.publisher.corporateUniversity of Calgaryeng
dc.publisher.facultyScienceeng
dc.subjectComputer Scienceeng
dc.titleTHE ARCHITECTURE OF HENDERSON'S SECD MACHINEeng
dc.typeunknown
thesis.degree.disciplineComputer Scienceeng
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