Browsing by Author "Zailer, Eugene"
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- ItemOpen AccessA Completely Integrated Warm-IF Receiver and a 10GS/s Analog-Delay Pipeline ADC for Radio-Telescope Applications(2019-05-22) Zailer, Eugene; Belostotski, Leonid; Plume, René; Helaoui, Mohamed; Vyas, Rushi J.; Brown, Jo C.; Saavedra, Carlos E.The Cerro Chajnantor Atacama Telescope (CCAT) Heterodyne Array Instrument (CHAI) radio-telescope is a large international effort involving University of Calgary, Kölner Observatorium für Sub-Millimeter Astronomie (KOSMA), University of Bonn, McGill University, and many others. The goal of the CHAI project is to upgrade the existing telescope capabilities to receive high-resolution images specifically in the 460 GHz and 830 GHz bands. The intended receiver system will have 128 (up to 256) antenna elements each requiring 128 independent receivers to be used. The Square Kilometer Array (SKA) is another major global effort to create the most sensitive radio telescope ever attempted. This radio telescope involves more than a hundred universities as well as industry. The SKA will potentially require millions of antenna elements, each requiring a cost-effective receiver to be implemented. This thesis presents a study of using a cost-effective CMOS technology to implement a complete receiver integrated on a single chip for CHAI and SKA telescopes. A receiver including a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), a mixer, and a variable-gain amplifier (VGA), based on CHAI design requirements, was implemented in 0.13 μm complementary metal-oxide semiconductor (CMOS) technology. An analog-to-digital converter (ADC) was implemented, based on the design requirements of the SKA, in 65 nm CMOS technology. A novel method for LNA wide-band noise optimization is developed and implemented in 0.13 μm CMOS technology. The design of the LNA is verified experimentally and meets the design requirements set by the CCAT project specifications. The LNA achieves a noise figure (NF) of <2.4 dB over the intended band of 4 GHz to 8 GHz with a gain of 18 dB. A novel method for VCO phase-noise (PN) optimization that simultaneously reduces VCO die-area and increases the available tuning range, was developed. The VCO is implemented in 0.13 μm CMOS technology and the novel optimization method is verified experimentally. The measured PN at 8 GHz is -134.3 dBc/Hz at a 1 MHz offset with a figure-of-merit (FOM) of 204 dBc/Hz. The ADC is developed using a novel topology that improves the speed performance of sub-ranging ADCs by removing the bottleneck and allowing both ADCs to run at full speed.
- ItemOpen AccessMethod of Generating Unique Elementary Circuit Topologies Méthode de génération de topologies de circuits élémentaires uniques(Institute of Electrical and Electronics Engineers, 2018-01) Shahhosseini, Delaram; Zailer, Eugene; Behjat, Laleh; Belostotski, LeonidDesigning analog circuits with new topologies is often very challenging, as it requires not only circuit design expertise but also an intuition of how various elementary circuits may work when put together to form a larger circuit. In this paper, we present a method of generating all functional elementary circuit topologies. The paper uses combinatorics to ensure that all unique circuit topologies are generated and stored in a database. This database contains 582 two-transistor and 56,280 three-transistor functional and unique elementary circuit topologies. It is envisioned that the circuit topologies stored in the database can save design time and assist designers by both offering previously unknown circuit topologies and providing circuit topologies for further optimizations. To give an example of how this vision can be used in practice, a search for all amplifier circuits was conducted that resulted in 5,177 circuit topologies, some previously unknown, out of 56,862 three-transistor elementary circuit topologies.
- ItemOpen AccessWideband LNA Noise Matching(2020-01) Zailer, Eugene; Belostotski, Leonid; Plume, RenéA new method for designing wideband noise- and power-matched source-degenerated cascode LNAs is presented. At the core of the method is the selection of transistor size and biasing that simultaneously minimize the difference between the LNA noise factor and the minimum noise factor as well as reduce the sensitivity of that difference to frequency. An experimental demonstration of the method is presented with a 0.13-μm CMOS LNA exhibiting <-12dB S11, 10dB of gain, and <2.5dB NF, which remains within 2.8% of the minimum noise figure, from 4 to 8GHz while consuming 12.8mW of power.