A Fast Locking Scheme for PLL Frequency Synthesizers
Date
2013-09-24
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Abstract
This thesis presents a fast-locking technique and architecture for phase-locked-loop{based
frequency synthesizers. To obtain a fast acquisition behaviour, the output signal frequency
is preset in advance. Within two cycles after frequency preset the phase di erence at the
input of the phase-frequency detector is coarsely compensated with the aid of a digital delay-
locked loop. The remainder of the phase di erence is compensated by the charge-pump PLL.
The roughly synchronized signal takes negligible time to settle. The proposed architecture
and technique were utilized in the design of a 1-GHz on-chip frequency synthesizer. The
veracity of the proposed technique and architecture is studied through simulations in the
TSMC 65-nm CMOS technology schematic simulation. As a proof of the concept, a discrete
frequency synthesizer is constructed and measurements carried out in order to illustrate the
acquisition process and its superiority to conventional synthesizers. As simulated in 65-nm
CMOS technology, the frequency synthesizer consumes 12 mW dc power. At 1 GHz the
output's peak-to-peak jitter is 11 ps and its rms jitter is 1.9 ps.
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Electronics and Electrical
Citation
Naji, A. (2013). A Fast Locking Scheme for PLL Frequency Synthesizers (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/24734