Mixed mode ic implementation for a robot path planner
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2011
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Abstract
This thesis presents a study of a unique hybrid processor for a unique path-planning algorithm, which has already been proved successful. The architecture is a serial approach towards the algorithm using one analog multiplier embedded in a digital processor to do the calculations. It was shown that the IC implementation of this algorithm is very robust and works with all hardware deficiencies around it (noise in the multiplier, quantization noise in the data converters etc). The power consumption and chip area (without the data converters) of this implementation was less than 50 n W and 0.5 mm2 respectively.
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Bibliography: p. 209-213
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Citation
Naik, M. (2011). Mixed mode ic implementation for a robot path planner (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/3993