Reconfigurable digital filter compiler
Date
2012
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Abstract
The availability of small, low-power, low-cost FPGAs make them appealing for the implementation of reconfigurable digital filters in audio signal processing applications. A Digital Signal Processing (DSP) unit with a Multiply-Accumulate (MAC) core can be used to implement digital filters where the arithmetic operations required occur sequentially. The speed and limited resources of low-cost FPGAs limit the number of operations available to implement the digital filter.
This thesis presents a reconfigurable digital filter compiler used to generate configuration data for a reconfigurable DSP unit used to implement a digital filter. The filter compiler automatically generates filter configurations that reduce the number of required operations to implement the digital filter. The finite-precision effects of the selected filter configuration on the magnitude frequency response are presented, allowing the user to choose an acceptable configuration.
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Bibliography: p. 125-128
Many pages are in colour.
Many pages are in colour.
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Citation
Manderson, T. (2012). Reconfigurable digital filter compiler (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/4766