Reliability analysis of logic networks
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AbstractThe reliability of digital devices is threatened by various sources, ranging from architectural issues and process variations to environmental fluctuations and noises. Also, error generated by these sources are inherently stochastic and transient. This makes reliability analysis an indispensable step of circuit design. Several reliability evaluation methods have been proposed for binary logic circuit. However, correlation of reliability with the input and gate errors and reliability analysis of multivalued circuits have not been investigated as of yet. This research investigates the reliability of switching circuits based on probabilistic models, and examines their applicability to multivalued circuits. We also develop an algebraic method for evaluating reliability of multivalued circuits. We further discuss how reliability of k-ary logic networks depends on radix k, input and gate errors. Thereafter, we propose a probabilistic model for representing and detecting faults. This research also studies behavior of probabilistic logic networks for very large (continuous) radix.
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