A Serial Communication-Based FPGA Co-Emulation Test Bench
Date
2018-04-23
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
FPGA designs are verified first with the simulation testing on a computer to check their behavior, and next verified with the emulation tested in an actual FPGA system to check its functional and timing performance. Co-emulation technology has been introduced to combine the simulation and emulation verification into one step which verifies the design by running the simulation test case directly on an FPGA board. Current co-emulation test benches accelerate the verification speed but need complex hardware to support its parallel communication interface. This research proposes to replace the parallel communication interface with a serial design to reduce the complexity of the hardware design. According to this proposal, the thesis introduces the hierarchy and architecture of the serial communication-based co-emulation test framework. It develops the proposed test bench based on the framework. Finally, it demonstrates the simulation and co-emulation test result to prove the feasibility of the proposed test bench
Description
Keywords
FPGA Co-emulation, FPGA Co-emulation test bench, Serial communication-based test bench
Citation
Cao, D. (2018). A Serial Communication-Based FPGA Co-Emulation Test Bench (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/31822