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THE VLSI IMPLEMENTATION OF A FINE-GRAINED PARALLEL ARCHITECTURE

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Author
Williams, Simon Richard
Accessioned
2008-02-26T23:04:23Z
Available
2008-02-26T23:04:23Z
Computerscience
1999-05-27
Issued
1990-06-01
Subject
Computer Science
Type
unknown
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Abstract
This thesis evolved out of a fine-grained parallel processor designed by John Cleary. The design was improved to increase the speed and provide testability. The resultant design was then implemented as a VLSI layout. Estimates of power consumption and clocking speeds were then derived from the layout using SPICE simulations. Evaluation shows that the power estimate is within practical limits of chip operation when packaged. Issues of fanout, metal migration, and supply line noise are also addressed.
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We are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at digitize@ucalgary.ca
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University of Calgary
Faculty
Science
Doi
http://dx.doi.org/10.11575/PRISM/31129
Uri
http://hdl.handle.net/1880/45694
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