Abstract
This thesis evolved out of a fine-grained parallel processor designed
by John Cleary. The design was improved to increase the speed and
provide testability. The resultant design was then implemented as a
VLSI layout. Estimates of power consumption and clocking speeds
were then derived from the layout using SPICE simulations. Evaluation
shows that the power estimate is within practical limits of chip
operation when packaged. Issues of fanout, metal migration, and
supply line noise are also addressed.
Notes
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