CMOS Realization of All-Positive Pinched Hysteresis Loops

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2017-08-06
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Abstract

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.

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B. J. Maundy, A. S. Elwakil, and C. Psychalinos, “CMOS Realization of All-Positive Pinched Hysteresis Loops,” Complexity, vol. 2017, Article ID 7863095, 15 pages, 2017. doi:10.1155/2017/7863095