THE VLSI IMPLEMENTATION OF A FINE-GRAINED PARALLEL ARCHITECTURE

dc.contributor.authorWilliams, Simon Richardeng
dc.date.accessioned2008-02-26T23:04:23Z
dc.date.available2008-02-26T23:04:23Z
dc.date.computerscience1999-05-27eng
dc.date.issued1990-06-01eng
dc.description.abstractThis thesis evolved out of a fine-grained parallel processor designed by John Cleary. The design was improved to increase the speed and provide testability. The resultant design was then implemented as a VLSI layout. Estimates of power consumption and clocking speeds were then derived from the layout using SPICE simulations. Evaluation shows that the power estimate is within practical limits of chip operation when packaged. Issues of fanout, metal migration, and supply line noise are also addressed.eng
dc.description.notesWe are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at digitize@ucalgary.caeng
dc.identifier.department1990-391-15eng
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/31129
dc.identifier.urihttp://hdl.handle.net/1880/45694
dc.language.isoEngeng
dc.publisher.corporateUniversity of Calgaryeng
dc.publisher.facultyScienceeng
dc.subjectComputer Scienceeng
dc.titleTHE VLSI IMPLEMENTATION OF A FINE-GRAINED PARALLEL ARCHITECTUREeng
dc.typeunknown
thesis.degree.disciplineComputer Scienceeng
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