Belostotski, LeonidPlume, RenéZailer, Eugene2019-05-302019-05-302019-05-22Zailer, E. (2019). A Completely Integrated Warm-IF Receiver and a 10GS/s Analog-Delay Pipeline ADC for Radio-Telescope Applications (Doctoral thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca.http://hdl.handle.net/1880/110446The Cerro Chajnantor Atacama Telescope (CCAT) Heterodyne Array Instrument (CHAI) radio-telescope is a large international effort involving University of Calgary, Kölner Observatorium für Sub-Millimeter Astronomie (KOSMA), University of Bonn, McGill University, and many others. The goal of the CHAI project is to upgrade the existing telescope capabilities to receive high-resolution images specifically in the 460 GHz and 830 GHz bands. The intended receiver system will have 128 (up to 256) antenna elements each requiring 128 independent receivers to be used. The Square Kilometer Array (SKA) is another major global effort to create the most sensitive radio telescope ever attempted. This radio telescope involves more than a hundred universities as well as industry. The SKA will potentially require millions of antenna elements, each requiring a cost-effective receiver to be implemented. This thesis presents a study of using a cost-effective CMOS technology to implement a complete receiver integrated on a single chip for CHAI and SKA telescopes. A receiver including a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), a mixer, and a variable-gain amplifier (VGA), based on CHAI design requirements, was implemented in 0.13 μm complementary metal-oxide semiconductor (CMOS) technology. An analog-to-digital converter (ADC) was implemented, based on the design requirements of the SKA, in 65 nm CMOS technology. A novel method for LNA wide-band noise optimization is developed and implemented in 0.13 μm CMOS technology. The design of the LNA is verified experimentally and meets the design requirements set by the CCAT project specifications. The LNA achieves a noise figure (NF) of <2.4 dB over the intended band of 4 GHz to 8 GHz with a gain of 18 dB. A novel method for VCO phase-noise (PN) optimization that simultaneously reduces VCO die-area and increases the available tuning range, was developed. The VCO is implemented in 0.13 μm CMOS technology and the novel optimization method is verified experimentally. The measured PN at 8 GHz is -134.3 dBc/Hz at a 1 MHz offset with a figure-of-merit (FOM) of 204 dBc/Hz. The ADC is developed using a novel topology that improves the speed performance of sub-ranging ADCs by removing the bottleneck and allowing both ADCs to run at full speed.engUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.Radio TelescopeIntegrated CircuitReceiverAstronomy and AstrophysicsEngineering--Electronics and Electricaldoctoral thesis10.11575/PRISM/36605