Shahhosseini, DelaramZailer, EugeneBehjat, LalehBelostotski, Leonid2022-10-272022-10-272018-01Shahhosseini, Zailer, E., Behjat, L., and Belostotski, L. (2018). Method of Generating Unique Elementary Circuit Topologies Méthode de génération de topologies de circuits élémentaires uniques. Canadian Journal of Electrical and Computer Engineering, 41(3), 118–132. https://doi.org/10.1109/CJECE.2018.28596210840-8688http://hdl.handle.net/1880/115382https://doi.org/10.11575/PRISM/46034Designing analog circuits with new topologies is often very challenging, as it requires not only circuit design expertise but also an intuition of how various elementary circuits may work when put together to form a larger circuit. In this paper, we present a method of generating all functional elementary circuit topologies. The paper uses combinatorics to ensure that all unique circuit topologies are generated and stored in a database. This database contains 582 two-transistor and 56,280 three-transistor functional and unique elementary circuit topologies. It is envisioned that the circuit topologies stored in the database can save design time and assist designers by both offering previously unknown circuit topologies and providing circuit topologies for further optimizations. To give an example of how this vision can be used in practice, a search for all amplifier circuits was conducted that resulted in 5,177 circuit topologies, some previously unknown, out of 56,862 three-transistor elementary circuit topologies.eng© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Computer-Aided DesignAnalog Circuit SynthesisIntegrated Circuit DesignMathematical programmingCircuit topologiesMethod of Generating Unique Elementary Circuit Topologies Méthode de génération de topologies de circuits élémentaires uniquesjournal articlehttp://dx.doi.org/10.1109/CJECE.2018.2859621