Smith, Michael RichardCao, Dingcheng2018-04-252018-04-252018-04-23Cao, D. (2018). A Serial Communication-Based FPGA Co-Emulation Test Bench (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/31822http://hdl.handle.net/1880/106536FPGA designs are verified first with the simulation testing on a computer to check their behavior, and next verified with the emulation tested in an actual FPGA system to check its functional and timing performance. Co-emulation technology has been introduced to combine the simulation and emulation verification into one step which verifies the design by running the simulation test case directly on an FPGA board. Current co-emulation test benches accelerate the verification speed but need complex hardware to support its parallel communication interface. This research proposes to replace the parallel communication interface with a serial design to reduce the complexity of the hardware design. According to this proposal, the thesis introduces the hierarchy and architecture of the serial communication-based co-emulation test framework. It develops the proposed test bench based on the framework. Finally, it demonstrates the simulation and co-emulation test result to prove the feasibility of the proposed test benchengUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.FPGA Co-emulationFPGA Co-emulation test benchSerial communication-based test benchComputer ScienceEngineering--Electronics and Electricalmaster thesis10.11575/PRISM/31822