Yanushkevich, SvetlanaMohamed, Tamer2013-04-302013-06-102013-04-302013http://hdl.handle.net/11023/656This work investigates techniques for building fault-tolerant digital circuits at the nano-scale. It provides an overview of some nano-scale technology candidates that can be used in the next generation of digital circuit based on nanoelectronic logic fabrics. It focuses on fault tolerance of such circuits at both the circuit and the architecture level. A case study based on pass-transistor logic using wrap-gate nanowire devices is presented. Such circuits implement logic computing in the form of binary decision diagrams (BDDs), however, they are not fault-immune. In this thesis, the BDD based nanowire devices that incorporate error correction coding are proposed. In addition, a planarization algorithm is presented and implemented in order to synthesize planar error correcting circuits using such devices. Alternative architecture, such as the cross-bar nano-FPGA, is considered as another candidate for fault-tolerance. Simulation and modeling of all the presented architectures are performed using the developed software "BDD processing tool", CUDD package and SPICE.engUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.Engineering--Electronics and ElectricalFault-toleranceNanoarchitectureBinary-Decision-Diagramsdoctoral thesis10.11575/PRISM/26166