Synthesis of digital signal processing systems using pipelined bit-serial arithmetic

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dc.contributor.advisorTurner, Laurence E.
dc.contributor.authorNagalla, Radhakrishna
dc.date.accessioned2005-07-27T23:34:34Z
dc.date.available2005-07-27T23:34:34Z
dc.date.issued1991
dc.descriptionBibliography: p. 121-124.en
dc.format.extentxii, 139 leaves ; 30 cm.en
dc.identifier.citationNagalla, R. (1991). Synthesis of digital signal processing systems using pipelined bit-serial arithmetic (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/12874en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/12874
dc.identifier.isbn0315751401en
dc.identifier.lccTK 5102.5 N34 1991en
dc.identifier.urihttp://hdl.handle.net/1880/24583
dc.language.isoeng
dc.publisher.institutionUniversity of Calgaryen
dc.publisher.placeCalgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subject.lccTK 5102.5 N34 1991en
dc.subject.lcshSignal processing - Digital techniques
dc.subject.lcshDigital electronics
dc.subject.lcshIntegrated circuits - Very large scale integration - Design and construction
dc.subject.lcshComputer architecture
dc.titleSynthesis of digital signal processing systems using pipelined bit-serial arithmetic
dc.typemaster thesis
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorUniversity of Calgary
thesis.degree.nameMaster of Science (MSc)
ucalgary.item.requestcopyfalse
ucalgary.thesis.notesoffsiteen
ucalgary.thesis.uarcreleaseyen
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