The VLSI implementation of a fine-grained parallel architecture

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dc.contributor.advisorCleary, John G.
dc.contributor.authorWilliams, Simon Richard
dc.date.accessioned2005-07-21
dc.date.available2005-07-21
dc.date.issued1990
dc.descriptionBibliography: p. 95-98.en
dc.format.extentxi, 137 leaves : ill. ; 30 cm.en
dc.identifier.citationWilliams, S. R. (1990). The VLSI implementation of a fine-grained parallel architecture (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/20080en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/20080
dc.identifier.isbn0315617004en
dc.identifier.lccQA 76.5 W555 1990en
dc.identifier.urihttp://hdl.handle.net/1880/17963
dc.language.isoeng
dc.publisher.institutionUniversity of Calgaryen
dc.publisher.placeCalgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subject.lccQA 76.5 W555 1990en
dc.subject.lcshIntegrated circuits - Very large scale integration
dc.subject.lcshParallel processing (Electronic computers)
dc.titleThe VLSI implementation of a fine-grained parallel architecture
dc.typemaster thesis
thesis.degree.disciplineComputer Science
thesis.degree.grantorUniversity of Calgary
thesis.degree.nameMaster of Science (MSc)
ucalgary.thesis.accessionTheses Collection 58.002:Box 765 520535207
ucalgary.thesis.notesoffsiteen
ucalgary.thesis.uarcreleaseyen
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