Browsing by Author "Madanayake, Arjuna"

Now showing 1 - 6 of 6
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    A 2-D Signal Processing Model to Predict the Effect of Mutual Coupling on Array Factor
    (IEEE, 2013-09) Kota, John; Madanayake, Arjuna; Belostotski, Leonid; Wijenayake, Chamith; Bruton, Len T.
    A semi-analytical method for modeling the effects of electromagnetic mutual coupling in uniform linear array (ULA) of N antennas is proposed. The coupling is described as a two-dimensional (2-D) spatiotemporal transfer function derived from S-parameter measurements. The proposed 2-D transfer function enables prediction of the distortions in array factor due to coupling, and thereby enables the potential design of coupling-compensation algorithms. The method is verified with simulations in the 1.5-2.0-GHz range on both an N=7-element ULA using CST Microwave Studio using 50- Ω terminations and a N=3-element ULA in FEKO but with non-50 Ω impedance obtained from measurements of a CMOS low noise amplifier (LNA). Coupling effect on array factor of delay-sum-type beamformer was examined. The proposed model matches within an error of 4%-12% and 4%-10% with respect to the results from two full-wave electromagnetic simulators CST Microwave Studio and FEKO, respectively, in the frequency range 1.75-2 GHz.
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    A New 2nd–Order Allpass Filter in 130nm CMOS
    (IEEE, 2016-09) Ahmadi, Peyman; Maundy, Brent; Elwakil, A.S.; Belostotski, Leonid; Madanayake, Arjuna
    This brief presents a novel wide-bandwidth second-order voltage-mode all-pass filter derived from a canonical single transistor bandpass filter. The core of the circuit consists of only one transistor, two resistors, and two energy storage elements. The operation of the proposed filter is validated experimentally. A filter implemented in an IBM 0.13-μm CMOS was measured to have a 55-ps group delay across a 6-GHz bandwidth while consuming 18.5 mW from a 1.5-V supply. This work experimentally demonstrates a CMOS all-pass filter that operates at multigigahertz frequencies and achieves the highest delay-bandwidth product compared to previously published CMOS all-pass filters known to the authors.
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    Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA
    (2013-04-03) Rajapaksha, Nilanka; Edirisuriya, Amila; Madanayake, Arjuna; Cintra, Renato J.; Onen, Dennis; Amer, Ihab; Dimitrov, Vassil S.
    Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65 nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracyimprovements obtained.
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    Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters
    (2012-09-17) Kondapalli, Soumya; Madanayake, Arjuna; Bruton, Len
    A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architecturesfor 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulatedand both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded for K-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metrics AT and AT2. The L2 error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits.
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    FPGA architectures for 2D/3D digital filters
    (2004) Madanayake, Arjuna; Bruton, Leonard T.
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    Real-time fpga architectures for space-time frequency-planar mdsp
    (2008) Madanayake, Arjuna; Bruton, Leonard T.