Browsing by Author "Schediwy, Rich"
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- ItemOpen AccessHARDWARE VERIFICATION BY FORMAL PROOF(1988-10-01) Birtwistle, Graham; Graham, Brian; Melham, Tom; Schediwy, RichHardware verification is the art of proving formally that, to within the tolerance of an underlying model, a design meets (or perhaps does not meet) its specification. This paper is an introduction to hardware verification and its limitations. We illustrate the technique by specifying and verifying an $x$ or gate and a ripple carry sub-system using the HOL notation, (see [2,8,9]), and then demonstrate its capabilities with sample applications to VLSI CAD and system re-implementation.