We explain and document the architecture of an eager SECD machine
devised by Henderson. A software interpreter for this architecture
has been in use for two years and has been well tested. Expansion of
the interpreter leads to the detailed specifications of an architecture
in VLSI. Such an SECD chip has been layed out and fabricated.
We are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at firstname.lastname@example.org