THE IMPLEMENTATION AND VERIFICATION OF A CONDITIONAL SUM ADDER

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dc.contributor.authorHan, Jungangeng
dc.contributor.authorStone, Gleneng
dc.date.accessioned2008-05-20T23:27:39Z
dc.date.available2008-05-20T23:27:39Z
dc.date.computerscience1999-05-27eng
dc.date.issued1988-07-01eng
dc.description.abstractIn this paper we first formulate the Conditional Sum Addition (CSA) algorithm, then design an area-time efficient Conditional Sum Adder in CMOS. We also design a Binary Look-ahead Carry adder and a fast ripple carry adder in the same technology for the comparison of their performances. Finally we formally prove that the CMOS implementation of the CSA adder is correct (i.e. the implementation meets the specification of the intended behavior) by using Mike Gordon's Higher Order Logic (HOL) system.eng
dc.description.notesWe are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at digitize@ucalgary.caeng
dc.identifier.department1988-311-23eng
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/31373
dc.identifier.urihttp://hdl.handle.net/1880/46505
dc.language.isoEngeng
dc.publisher.corporateUniversity of Calgaryeng
dc.publisher.facultyScienceeng
dc.subjectComputer Scienceeng
dc.titleTHE IMPLEMENTATION AND VERIFICATION OF A CONDITIONAL SUM ADDEReng
dc.typeunknown
thesis.degree.disciplineComputer Scienceeng
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