Self-timed bit-serial architectures for digital signal processing

dc.contributor.advisorTurner, Laurence E.
dc.contributor.authorLi, Jianchuan
dc.date.accessioned2017-12-18T21:02:33Z
dc.date.available2017-12-18T21:02:33Z
dc.date.issued2005
dc.descriptionBibliography: p. 91-95en
dc.format.extentxi, 95 leaves : ill. ; 30 cm.en
dc.identifier.citationLi, J. (2005). Self-timed bit-serial architectures for digital signal processing (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/156en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/156
dc.identifier.urihttp://hdl.handle.net/1880/101157
dc.language.isoeng
dc.publisher.institutionUniversity of Calgaryen
dc.publisher.placeCalgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.titleSelf-timed bit-serial architectures for digital signal processing
dc.typemaster thesis
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorUniversity of Calgary
thesis.degree.nameMaster of Science (MSc)
ucalgary.thesis.accessionTheses Collection 58.002:Box 1589 520492106
ucalgary.thesis.notesUARCen
ucalgary.thesis.uarcreleaseyen
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