CMOS Parametric Receiver Design for Short-Range and High Data-Rate Wireless Communication

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dc.contributor.advisorMagierowski, Sebastian
dc.contributor.advisorBelostotski, Leonid
dc.contributor.authorZhao, Zhixing
dc.contributor.committeememberOkoniewski, Michal
dc.contributor.committeememberHelaoui, Mohamed
dc.contributor.committeememberBarzanjeh, Shabir
dc.contributor.committeememberSaavedra, Carlos
dc.date2021-06
dc.date.accessioned2021-03-25T15:14:12Z
dc.date.available2021-03-25T15:14:12Z
dc.date.issued2021-02-03
dc.description.abstractWith the advent of 5G era, millimeter-wave technologies are drawing increased attention for fast-data-rate communication. Massive RF nodes deployments in 5G require inexpensive RF solutions. Recent RF developments associated with CMOS technologies promise to fulfill such requirements. However, millimeter-wave circuitry on CMOS is still expensive because achieving sufficient power gain requires advanced and costly CMOS nodes. In addition, the conventional way of seeking performance improvements, i.e. reliance on Moore’s law, is approaching its physical limits. In this thesis, parametric circuitry, as an alternative to RF performance enhancement at less-advanced nodes, is investigated. The parametric circuitry exploits varying capacitance to channel RF signal power from one frequency to another. During this frequency translation, an oscillator signal (known as Pump) power is added to the RF signal of interest so that the power gain is realized. The method is unlike a conventional transistor-based amplifier, which is essentially a DC-to-AC power converter. In addition to frequencies, the power gain of the parametric circuit can be tuned by the Pump signal as well. In this thesis, firstly the key technology, i.e. a variable capacitor, on CMOS technology is introduced and discussed. Then, the linearity of a CMOS 1-to-36 GHz parametric upconverter is analyzed. The agreement of the measurement and simulation results with the outcome of the analytic analysis demonstrates that the proposed harmonic analysis method can be relied on for the first-order analysis and quick grasp of design insights. Later, a sub-6GHz parametric downconverter is presented with a power gain of 24 dB. This circuit design shows a promising means to deploy parametric circuits at low-frequency bands.en_US
dc.identifier.citationZhao, Z. (2021). CMOS Parametric Receiver Design for Short-Range and High Data-Rate Wireless Communication (Doctoral thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca.en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/38693
dc.identifier.urihttp://hdl.handle.net/1880/113176
dc.language.isoengen_US
dc.publisher.facultySchulich School of Engineeringen_US
dc.publisher.institutionUniversity of Calgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.en_US
dc.subjectparametric circuit, CMOS, wireless communicationen_US
dc.subject.classificationEngineering--Electronics and Electricalen_US
dc.titleCMOS Parametric Receiver Design for Short-Range and High Data-Rate Wireless Communicationen_US
dc.typedoctoral thesisen_US
thesis.degree.disciplineEngineering – Electrical & Computeren_US
thesis.degree.grantorUniversity of Calgaryen_US
thesis.degree.nameDoctor of Philosophy (PhD)en_US
ucalgary.item.requestcopytrueen_US
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