Memory Consistency Models of Bus-Based Multiprocessors

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dc.contributor.authorHigham, L.eng
dc.contributor.authorKawash, J.eng
dc.date.accessioned2008-02-27T22:14:02Z
dc.date.available2008-02-27T22:14:02Z
dc.date.computerscience1999-12-29eng
dc.date.issued1996-10-01eng
dc.description.abstractThe Partial Orders Framework [3] provides a unified way to specify the memory semantics of distributed systems. This report demonstrates the usefulness of this framework for reasoning about the behavior of the shared memory of existing multiprocessors. Three bus-based machine models are examined: total ordering, total store ordering, and partial store ordering. A formal and unambiguous description of their memory consistency models is established using the unifying framework. The influence of caches on the memory is also investigated.eng
dc.description.notesWe are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at digitize@ucalgary.caeng
dc.identifier.department1996-594-14eng
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/30829
dc.identifier.urihttp://hdl.handle.net/1880/45990
dc.language.isoEngeng
dc.publisher.corporateUniversity of Calgaryeng
dc.publisher.facultyScienceeng
dc.subjectComputer Scienceeng
dc.titleMemory Consistency Models of Bus-Based Multiprocessorseng
dc.typeunknown
thesis.degree.disciplineComputer Scienceeng
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