Automating Asset Identification in SystemVerilog Hardware Designs

Nath, Subroto Kumer Deb

Automating Asset Identification in SystemVerilog Hardware Designs

dc.contributor.advisor	Tan, Benjamin
dc.contributor.author	Nath, Subroto Kumer Deb
dc.contributor.committeemember	Karimipour, Hadis
dc.contributor.committeemember	Ye, Qiang John
dc.date	2025-02
dc.date.accessioned	2025-01-30T15:40:43Z
dc.date.available	2025-01-30T15:40:43Z
dc.date.issued	2025-01-27
dc.description.abstract	The increasing complexity of hardware designs and the growing demand for secure systems have extended the responsibility of the designers. The early detection and mitigation of security flaws and vulnerabilities in the designs have increased the need for robust methodologies to identify and protect security-critical assets in the Register Transfer Level (RTL) source code. Knowing the security assets in a design is fundamental to downstream security analyses, such as threat modeling, weakness and attack point identification, and verification. This thesis presents two frameworks for automating the identification of potential primary security assets within RTL code in an Intellectual Property (IP) block. The asset identification process is traditionally performed manually and is highly resource-intensive. The first framework uses IP-specific keywords and behavioral patterns we manually identified by analyzing open-source hardware designs. The second framework identifies the signal’s behavioral and structural patterns, flow, and distribution throughout an IP block. We apply both frameworks to open-source hardware design projects and explore the outcomes. Through complex algorithms and iterative refinement, the frameworks provide a potential set of primary security assets and thus help to reduce the manual search space.
dc.identifier.citation	Nath, Subroto K. D. (2025). Automating asset identification in SystemVerilog hardware designs (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca.
dc.identifier.uri	https://hdl.handle.net/1880/120619
dc.language.iso	en
dc.publisher.faculty	Graduate Studies
dc.publisher.institution	University of Calgary
dc.rights	University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subject	Hardware Security
dc.subject	Asset Identification
dc.subject	RTL
dc.subject	Verilog
dc.subject	SystemVerilog
dc.subject	Hardware Designs
dc.subject	SoC
dc.subject.classification	Engineering--Electronics and Electrical
dc.title	Automating Asset Identification in SystemVerilog Hardware Designs
dc.type	master thesis
thesis.degree.discipline	Engineering – Electrical & Computer
thesis.degree.grantor	University of Calgary
thesis.degree.name	Master of Science (MSc)
ucalgary.thesis.accesssetbystudent	I do not require a thesis withhold – my thesis will have open access and can be viewed and downloaded publicly as soon as possible.