TLSIM: a timing and logic digital circuit simulator

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dc.contributor.advisorGu, Jun
dc.contributor.authorShoham, Idan
dc.date.accessioned2005-08-05T16:33:25Z
dc.date.available2005-08-05T16:33:25Z
dc.date.issued1993
dc.descriptionBibliography: p. 120-124.en
dc.format.extentxiii, 124 leaves ; 30 cm.en
dc.identifier.citationShoham, I. (1993). TLSIM: a timing and logic digital circuit simulator (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/17693en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/17693
dc.identifier.isbn0315886285en
dc.identifier.lccTK 7872 L64 S56 1993en
dc.identifier.urihttp://hdl.handle.net/1880/30811
dc.language.isoeng
dc.publisher.facultyEngineering
dc.publisher.institutionUniversity of Calgaryen
dc.publisher.placeCalgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subject.lccTK 7872 L64 S56 1993en
dc.subject.lcshLogic design
dc.subject.lcshProgrammable logic devices
dc.titleTLSIM: a timing and logic digital circuit simulator
dc.typemaster thesis
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorUniversity of Calgary
thesis.degree.nameMaster of Science (MSc)
ucalgary.thesis.accessionTheses Collection 58.002:Box 894 520541798
ucalgary.thesis.notesoffsiteen
ucalgary.thesis.uarcreleaseyen
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