A CMOS cell architecture and library

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dc.contributor.advisorBirtwistle, Graham M.
dc.contributor.authorSchediwy, Richard Robert
dc.date.accessioned2005-07-21T21:48:20Z
dc.date.available2005-07-21T21:48:20Z
dc.date.issued1986
dc.descriptionBibliography: p. 138-142.en
dc.description.abstractOne of the major problems faced in VLSI chip design is the potential for overwhelming complexity. Design complexity brings with it long design cycles and wide margins for error. This thesis has developed a partial solution to the problem in the form of a cell library and its associated methodology. A variety of primitive CMOS circuit elements have been designed with generality and longevity in mind. Experience has shown that, when using these cells, the penalties paid in area, power and delay are tolerable. Indeed, the penalties are more than compensated by very rapid design times, process independence and design longevity. The primitive cells are composable into more complex elements, sub-systems and ultimately, complete chips. Primitive cells are designed on a fine grid tuned to generalized CMOS lambda rules. By restricting their borders, port positions and interconnect style, we can abstract all lambda dependent design rule details away at higher levels. Thus, at the composition level, we can work entirely on a coarser grid with the guarantee of being free from lambda design rule errors. The composition rules for the coarse grid are few, simple and easy to enforce. Sub-systems thus composed are regular and compatible and may be retained for use as primitives in the library. The associated methodology provides a top-down design style which can be consistently applied to designing new primitive cells and to composing new sub-systems. It eases some of the problems of complex design by supporting abstraction and composition. The methodology is easy to learn by beginners, easy to use and provides a fundamental broad base for design automation tools. Several chips designed using this methodology have been fabricated and tested. The library is now an established component of the Electric design system and is available through MOS IS.
dc.format.extentxi, 178 leaves : ill. ; 30 cm.en
dc.identifier.citationSchediwy, R. R. (1986). A CMOS cell architecture and library (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/21788en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/21788
dc.identifier.isbn0315381108en
dc.identifier.lccTK 7871.99 M44 S34 1986en
dc.identifier.urihttp://hdl.handle.net/1880/23848
dc.language.isoeng
dc.publisher.institutionUniversity of Calgaryen
dc.publisher.placeCalgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subject.lccTK 7871.99 M44 S34 1986en
dc.subject.lcshMetal oxide semiconductors, Complementary
dc.subject.lcshIntegrated circuits - Very large scale integration
dc.titleA CMOS cell architecture and library
dc.typemaster thesis
thesis.degree.disciplineComputer Science
thesis.degree.grantorUniversity of Calgary
thesis.degree.nameMaster of Science (MSc)
ucalgary.item.requestcopytrue
ucalgary.thesis.notesoffsiteen
ucalgary.thesis.uarcreleaseyen
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