Method of Generating Unique Elementary Circuit Topologies Méthode de génération de topologies de circuits élémentaires uniques

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dc.contributor.authorShahhosseini, Delaram
dc.contributor.authorZailer, Eugene
dc.contributor.authorBehjat, Laleh
dc.contributor.authorBelostotski, Leonid
dc.date.accessioned2022-10-27T21:05:29Z
dc.date.available2022-10-27T21:05:29Z
dc.date.issued2018-01
dc.description.abstractDesigning analog circuits with new topologies is often very challenging, as it requires not only circuit design expertise but also an intuition of how various elementary circuits may work when put together to form a larger circuit. In this paper, we present a method of generating all functional elementary circuit topologies. The paper uses combinatorics to ensure that all unique circuit topologies are generated and stored in a database. This database contains 582 two-transistor and 56,280 three-transistor functional and unique elementary circuit topologies. It is envisioned that the circuit topologies stored in the database can save design time and assist designers by both offering previously unknown circuit topologies and providing circuit topologies for further optimizations. To give an example of how this vision can be used in practice, a search for all amplifier circuits was conducted that resulted in 5,177 circuit topologies, some previously unknown, out of 56,862 three-transistor elementary circuit topologies.en_US
dc.identifier.citationShahhosseini, Zailer, E., Behjat, L., and Belostotski, L. (2018). Method of Generating Unique Elementary Circuit Topologies Méthode de génération de topologies de circuits élémentaires uniques. Canadian Journal of Electrical and Computer Engineering, 41(3), 118–132. https://doi.org/10.1109/CJECE.2018.2859621en_US
dc.identifier.doihttp://dx.doi.org/10.1109/CJECE.2018.2859621en_US
dc.identifier.isbn0840-8688
dc.identifier.urihttp://hdl.handle.net/1880/115382
dc.identifier.urihttps://doi.org/10.11575/PRISM/46034
dc.language.isoengen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.publisher.departmentElectrical and Computer Engineeringen_US
dc.publisher.facultySchulich School of Engineeringen_US
dc.publisher.hasversionacceptedVersionen_US
dc.publisher.institutionUniversity of Calgaryen_US
dc.publisher.policyhttps://journals.ieeeauthorcenter.ieee.org/become-an-ieee-journal-author/publishing-ethics/guidelines-and-policies/post-publication-policies/#accepteden_US
dc.rights© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en_US
dc.subjectComputer-Aided Designen_US
dc.subjectAnalog Circuit Synthesisen_US
dc.subjectIntegrated Circuit Designen_US
dc.subjectMathematical programmingen_US
dc.subjectCircuit topologiesen_US
dc.titleMethod of Generating Unique Elementary Circuit Topologies Méthode de génération de topologies de circuits élémentaires uniquesen_US
dc.typejournal articleen_US
ucalgary.item.requestcopytrueen_US
ucalgary.scholar.levelFacultyen_US
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