Two dimensional IC layout compaction

dc.contributor.advisor	Birtwistle, Graham M.
dc.contributor.author	Liu, Erwin Sai Ki, 1955-
dc.date.accessioned	2005-07-21T21:39:17Z
dc.date.available	2005-07-21T21:39:17Z
dc.date.issued	1986
dc.description	Bibliography: p. 200-204.	en
dc.format.extent	xix, 204 leaves : ill. ; 30 cm.	en
dc.identifier.citation	Liu, E. S. (1986). Two dimensional IC layout compaction (Doctoral thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/16774	en_US
dc.identifier.doi	http://dx.doi.org/10.11575/PRISM/16774
dc.identifier.isbn	0315359900	en
dc.identifier.lcc	TK 7874 L58 1987	en
dc.identifier.uri	http://hdl.handle.net/1880/23746
dc.language.iso	eng
dc.publisher.institution	University of Calgary	en
dc.publisher.place	Calgary	en
dc.rights	University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subject.lcc	TK 7874 L58 1987	en
dc.subject.lcsh	Integrated circuits
dc.subject.lcsh	Electronic circuit design
dc.title	Two dimensional IC layout compaction
dc.type	doctoral thesis
thesis.degree.discipline	Computer Science
thesis.degree.grantor	University of Calgary
thesis.degree.name	Doctor of Philosophy (PhD)
ucalgary.thesis.notes	offsite	en
ucalgary.thesis.uarcrelease	y	en

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