Statistics for Power and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits
Total visits
| views | |
|---|---|
| Power and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits | 44 |
Total visits per month
| views | |
|---|---|
| September 2024 | 0 |
| October 2024 | 0 |
| November 2024 | 2 |
| December 2024 | 1 |
| January 2025 | 0 |
| February 2025 | 10 |
| March 2025 | 0 |
File Visits
| views | |
|---|---|
| ucalgary_2016_farshidi_amin.pdf | 36 |
Top country views
| views | |
|---|---|
| Canada | 43 |
Top city views
| views | |
|---|---|
| Calgary | 43 |