A Time-Based 5GS/s CMOS Analog-to-Digital Converter
Date
2013-06-03
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Abstract
In deep-submicron CMOS technology, the switching speed of digital circuits has become extremely fast. At the same time, analog design has become increasingly difficult due to very low supply voltage levels. This makes it advantageous to represent signals in the time-domain as the delay between two digital pulse edges, rather than the conventional voltage domain. This work applies the idea of time-based processing to high-speed analog-to-digital converters (ADCs).
The proposed time-based ADC consists of two stages. The first is the voltage-to-time converter (VTC), which uses a modified current-starved inverter architecture. The VTC accepts an analog voltage input and produces a series of pulses in which the delay of each pulse is proportional to the input at the time the pulse was created. The second stage is the time-to-digital converter (TDC). The TDC measures the delay on each VTC pulse and converts it to a digital logic value. The VTC and TDC can be physically separated with the VTC output transmitted to the TDC input over coaxial cables. An on-chip digital programming system in the TDC allows the entire ADC to be calibrated, and an automatic calibration scheme is presented.
Two prototypes were fabricated, a 3-bit 2.5GS/s ADC in 90nm CMOS and a 4-bit 5GS/s ADC in 65nm CMOS. The 65nm circuit achieves an effective resolution bandwidth of 2.1GHz and consumes 34.6mW of power. The figure of merit is 1.0pJ/conversion. This is the fastest time-based ADC published to date.
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Engineering--Electronics and Electrical
Citation
Macpherson, A. R. (2013). A Time-Based 5GS/s CMOS Analog-to-Digital Converter (Doctoral thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/25056