Methods for Solving Modern, Scale-Borne Problems in VLSI Physical Design
| atmire.migration.oldid | 404 | |
| dc.contributor.advisor | Behjat, Laleh | |
| dc.contributor.author | Rakai, Logan | |
| dc.date.accessioned | 2012-10-01T18:41:14Z | |
| dc.date.available | 2012-11-13T08:01:43Z | |
| dc.date.issued | 2012-10-01 | |
| dc.date.submitted | 2012 | en |
| dc.description.abstract | The design automation community is confronted with new challenges every technology node. Many of the challenges are borne out of issues relating to scale, be it the very small or the very large. For example, the extremely large scale of the number of instances in modern designs creates challenges in effectively exploring vast solution spaces in reasonable amounts of time. At the other end of the scale spectrum, the extremely small scale of features created by modern lithography processes are highly susceptible to process variations which affect performance and yield. This thesis deals with the development of methods for solving scale-borne problems in the physical design of integrated circuits. This thesis addresses challenges faced in two important phases of physical design: placement and clock network synthesis. The importance of these two phases is reflected in the fact that they have been the subject of five out of the last seven ACM/IEEE International Symposium on Physical Design (ISPD) contests. The number of instances and the size of the solution space in performing placement are truly immense. A proven linear-time clustering algorithm is proposed to deal with the explosion of problem sizes being encountered. Several extensions to the algorithm are proposed to further improve the quality of results. The number of instances in clock network design is also growing at a rapid pace. In order to cope with this challenge, a generic framework to parallelize algorithms that perform the main stages of clock network synthesis is proposed. Theorems are provided to prove asymptotically optimal speedup when the framework is applied to several classes of algorithms. Another challenge addressed regarding clock network synthesis is that of variation. A method is proposed for handling variations in lengths and widths of buffers and interconnects, that arise from the manufacturing process. | en_US |
| dc.identifier.citation | Rakai, L. (2012). Methods for Solving Modern, Scale-Borne Problems in VLSI Physical Design (Doctoral thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/26895 | en_US |
| dc.identifier.doi | http://dx.doi.org/10.11575/PRISM/26895 | |
| dc.identifier.uri | http://hdl.handle.net/11023/253 | |
| dc.language.iso | eng | |
| dc.publisher.faculty | Graduate Studies | |
| dc.publisher.institution | University of Calgary | en |
| dc.publisher.place | Calgary | en |
| dc.rights | University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission. | |
| dc.subject | Engineering--Electronics and Electrical | |
| dc.subject.classification | Computer-aided design | en_US |
| dc.subject.classification | Parallel algorithms | en_US |
| dc.subject.classification | Robust Optimization | en_US |
| dc.subject.classification | Clustering | en_US |
| dc.title | Methods for Solving Modern, Scale-Borne Problems in VLSI Physical Design | |
| dc.type | doctoral thesis | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Calgary | |
| thesis.degree.name | Doctor of Philosophy (PhD) | |
| ucalgary.item.requestcopy | true |