Ultra-Low Power Sub-Threshold Nanoscale CMOS Path Planning Cores
| atmire.migration.oldid | 851 | |
| dc.contributor.advisor | Magierowski, Sebastian | |
| dc.contributor.advisor | Haslett, Jim | |
| dc.contributor.author | Wu, Ryan | |
| dc.date.accessioned | 2013-04-25T16:37:30Z | |
| dc.date.available | 2013-06-10T07:00:44Z | |
| dc.date.issued | 2013-04-25 | |
| dc.date.submitted | 2013 | en |
| dc.description.abstract | This project aims to develop a specialized processor that is optimized for power and algorithm efficiency. The optimization would be targeted for a path-planning algorithm for micro- robots such as insect-bots, UAVs (unmanned aerial vehicles) and for nano-medicine. This processor would provide a computation platform that is smaller, lighter and more power efficient than conventional general-purpose processors to allow these micro-bots to reach a high level of intelligence. These micro-bots would then be able to navigate themselves to their destination, and perform simple tasks and data processing. To achieve this goal, the processor was designed using a custom computing architecture implemented in RTL, then synthesized and detailed designed to layouts that are then fabri- cated into a physical processor. The processor design target was to operate at 100kHz, while consuming only tens of microwatts and weighing only milligrams. | en_US |
| dc.identifier.citation | Wu, R. (2013). Ultra-Low Power Sub-Threshold Nanoscale CMOS Path Planning Cores (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/28545 | en_US |
| dc.identifier.doi | http://dx.doi.org/10.11575/PRISM/28545 | |
| dc.identifier.uri | http://hdl.handle.net/11023/626 | |
| dc.language.iso | eng | |
| dc.publisher.faculty | Graduate Studies | |
| dc.publisher.institution | University of Calgary | en |
| dc.publisher.place | Calgary | en |
| dc.rights | University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission. | |
| dc.subject | Computer Science | |
| dc.subject | Engineering--Electronics and Electrical | |
| dc.subject | Robotics | |
| dc.subject.classification | Sub-Threshold | en_US |
| dc.subject.classification | Processor | en_US |
| dc.subject.classification | 90nm | en_US |
| dc.subject.classification | Optimization | en_US |
| dc.subject.classification | Digital | en_US |
| dc.subject.classification | Path Planning | en_US |
| dc.subject.classification | Cadence | en_US |
| dc.subject.classification | Synopsys | en_US |
| dc.subject.classification | Design | en_US |
| dc.subject.classification | MIPS | en_US |
| dc.subject.classification | ASIC | en_US |
| dc.title | Ultra-Low Power Sub-Threshold Nanoscale CMOS Path Planning Cores | |
| dc.type | master thesis | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Calgary | |
| thesis.degree.name | Master of Science (MSc) | |
| ucalgary.item.requestcopy | true |